The present invention relates generally to the identification of individual semiconductor die on a semiconductor wafer, and more specifically to a method and apparatus for providing the identification based on values stored in a semiconductor memory.
During the semiconductor fabrication process wafers are subjected to a number of processing operations, such as layering, patterning doping and heat treating. It is desirable to track the wafer throughout the manufacturing process to prevent wafer mis-processing and to maintain an accurate record of the processing steps to which the wafer was subjected. To provide the necessary unique identification for each wafer, conventionally bar codes or other identifying indicia are printed or laser engraved on the wafer surface.
Bar codes consist of a number of spaced apart parallel lines of varying widths, with data encoded in the line width and the line spacing. As the wafer is processed through the fabrications steps, an optical probe scans the wafer in a direction normal to the bar code lines. An incident light beam in the probe is modulated by the bar code lines to produce a reflected beam that caries the unique signature of the scanned bar code. The reflected light beam is directed to and detected by an electro-optical detector such that the detected electronic signal represents the scanned bar code. The code is associated with the wafer and thus is utilized to track the wafer during the fabrication process steps. In lieu of bar codes, it is also known to use laser inscribed dots to identify the wafer.
It is also desirable to track each individual die of a wafer by associating each die with the source wafer, the manufacturing lot and/or the die site (i.e., the location of the dice on the wafer) identifier. This information can later be useful to track yields in a particular wafer region and to identify the source wafer and lot if the die later fails during testing or in the field. Although this information can be physically added to each die by a bar code or laser inscribed dots, as described above, this may not be done due to the added processing cost. Also, once the die is packaged, the identification information is lost unless the package is also marked. Typically, packages are marked with manufacturing lot information, but the lot identifier is identical for a large number of die and thus the lot information can be efficiently applied, by silk screening, for example, to all packages containing die from the same lot. However, including individual die identification information on each package is costly.
FIG. 1 illustrates a wafer 10 on which are formed a plurality of circuit dice 12. Although only four such dice 12 are illustrated in FIG. 1 for convenience, it is known by those skilled in the art that a considerably greater number of circuit dice could be formed in the wafer 10 as is conventional in the art. Disposed in one corner of each dice 12 is an identification element 16, such as a bar code or laser inscribed dots, as discussed above.
It is known to add programmable memory circuitry to individual die to provide an indicia for later identification of the die site, wafer and manufacturing lot. The circuitry is electrically programmed during the wafer test phase or physically programmed during wafer laser repair with a serial number or other unique identifier. Laser wafer repair is typically used to select working memory blocks from a wafer during the functional test process by trimming interconnects on the wafer. This process can also be used to program circuitry that can be used later to identify the device. The identifier can be read from the device after it is placed into service to determine the die site, wafer and/or lot from which the die was taken. However, adding such programmable circuitry adds cost because it requires die area, and may also increase the pin count and fabrication process complexity. For relatively inexpensive integrated circuits, the extra cost may not merit the advantages provided.
Random access memory devices, especially static random access memories, are well known in the art. Such devices are comprised of a plurality of memory cells, each cell storing a single bit of information in the form of a binary 1 or a binary 0. Each cell is a flip-flop positioned at the intersection of an array of row and column address lines, also referred to as wordlines and bitlines, respectively. Specifically, each cell is positioned at the intersection of a word line and a set of complimentary bit lines, that is, a bit line and an inverse bit line. These memory devices provide random access in the sense that each cell can be individually addressed for read and write operations as determined by an address provided to a row and column address decoder, that in turn selects the intended cell at the intersection of the row and column address lines. Generally, the row or wordline is selected first, enabling all the cells on the selected row. The bitline and the inverse bitline select the individual column bit from among the selected row of cells, for reading a bit from or writing a bit to the selected cell over the bitline and the inverse bitline.
FIG. 2 is an exemplary schematic of four such adjacent static random access (SRAM) cells 20, 21, 22 and 23 constituting an SRAM memory array 18, having n wordlines (wordline 0 to wordline n) and m bitlines (bitline 0 to bitline m). Each of the memory cells 20, 21, 22 and 23 comprises six metal-oxide field-effect transistors (MOSFETS) arranged as two cross-coupled complementary MOSFETS (i.e., CMOS) inverters. Each of the cells 20, 21, 22 and 23 includes the same basic components and functions in the same manner. Thus only the cell 20 is described in detail.
The cell 20 includes NMOS switching transistors 30 and 32 having their gate terminals connected to a wordline 0. Source and drain terminals of the transistor 30 are connected between a bitline 0 and a node 34. Source and drain terminals of the transistor 32 are connected between an inverse bitline 0 and a node 36. A first source/drain terminal of NMOS transistors 40 and 42 is connected to ground. A first source/drain terminal of PMOS transistors 46 and 48 is connected to a supply voltage, designated VDD. A second source/drain terminal of the transistors 40 and 42 is connected to a second source/drain terminal of the transistors 46 and 48 at the nodes 34 and 36, respectively. The node 34 is further connected to a gate terminal of each transistor 42 and 48. The node 36 is further connected to a gate terminal of each of the transistors 40 and 46.
In operation, the cross-coupling of the two CMOS inverters (where the first inverter comprises the transistors 40 and 46 with the node 34 serving as the output terminal, and the second inverter comprises the transistors 42 and 48 with the node 36 serving as the output terminal) creates a bistable device. If the output of the first inverter is high (that is, the transistor 46 is on, the transistor 40 is off and the voltage at the node 34 is high), the high voltage at the node 34 is provided as an input to the gate terminals of the transistors 42 and 48 that comprise the second inverter. As a result, the second inverter is driven low (that is, the transistor 48 is off, the transistor 42 is on and the voltage on the node 36 is low). The state of the cell 20 where the first inverter is high can be considered a xe2x80x9c1xe2x80x9d state. If the transistors 40, 42, 46 and 48 are in an opposite state to that described above, the first inverter output is low and the second inverter output is high. This state can be considered the xe2x80x9c0xe2x80x9d state for the cell 20. In the xe2x80x9c0xe2x80x9d state, the node 34 is low and the node 36 is high.
To write a bit to the cell 20, the wordline 0 is selected, turning on the transistors 30 and 32. The bitline 0 and the inverse bitline 0 are charged to opposite states by a writer-driver, not shown, to store the bit on the bitline 0 to the memory cell 20. If a xe2x80x9c1xe2x80x9d on the bitline 0 is to be stored, the transistor 48 is driven to an off state and the cross coupling drives the transistor 46 on. Thus the voltage at the node 34 goes high and a xe2x80x9c1xe2x80x9d is stored in the cell 20. The inverse bitline 0 is low as the node 36 is effectively grounded when the transistor 48 is off. A xe2x80x9c0xe2x80x9d is stored by placing a low voltage on the bitline 0 and a high voltage on the inverse bitline 0. These voltages drive the transistor 48 into conduction and the transistor 46 goes off, driving the node 34 to ground.
The bit stored in the memory cell 20 is read by selecting the wordline 0 and determining the difference between the voltage on the bitline 0 and the inverse bitline 0. A sense amplifier (not shown in FIG. 2) measures the voltage differential and provides an output bit representative of the stored bit.
To identify an individual integrated circuit or die, power is applied to a block of memory cells on the integrated circuit. In response, each of the memory cells assumes an initial state (either a binary one or a binary zero) that is relatively consistent for each power up. The states are determined and used to identify the integrated circuit.